The switched-capacitor (SC) techniques enable the design of various filters that can be realized in monolithic integrated circuits from using state-of-art MOS technology. By replacing the noisy physical resistors with the switched-capacitor pairs, one is likely to draw the conclusion that many of the conventional methods developed for active-RC filters can be directly adapted to SC filters.

However, this is not true when the effects of the amplifier dynamics, such as operational amplifier finite gain and bandwidth, have to be considered for the analysis of real-world switched-capacitor filters. Moreover, the analysis of SC filter is often complicated due to the fact that it requires continuous-time domain analysis for investigating the op-amp dynamics, while the general method of evaluating the filter transfer function is of discrete-time nature.

Besides the fuzziness in dynamic analysis of SC filters, other nonidealities such as clock feedthrough, channel charge injection, and device DC offset would also play important roles in blurring the sights of the engineers who try to distinguish their effects.

This article provides a step-by-step example of designing a lowpass switched-capacitor filter with 1.5 MHz bandwidth. It starts by looking into the theoretical-level design of the filter transfer function, followed by an accurate operation of dynamic range scaling and various capacitance assignment optimization techniques. Next, efforts are taken to investigate the effects of op amp nonidealities on the overall filter response. Later, a realistic macro-model for the op amp is built in order to simulate the complete SC filter in transistor-level.

**Target Specs**

For the purposes of this article, we are going to design a lowpass switched-capacitor filter with the following target specifications **(Table 1)** :

Given the specifications, the transfer function of the target filter can be derived by using Matlab. The Matlab programs are attached in the sidebar.

In this article, four different types of filters have been compared in order to choose the prototype that can be realized with the lowest order (i.e. minimum number of opamps). As shown in **Figure 1** , an elliptical lowpass filter with an order of six is the best choice. Note that the passband ripple is assumed 0.1 dB and the stopband gain is assumed -75dB in order to provide sufficient design margin for circuit implementations.

The elliptical filter has a transfer function as following:

The order of the filter is six, which indicates that a three-stage cascaded biquadratic (biquad) configuration is adequate to realize this lowpass filter. The magnitude vs. frequency response of the prototype elliptical filter as well as the the locations of zeros and poles in the Z-domain are shown in **Figure 2** .

*Click here for Figure 2a and Click here for Figure2b*

The values of zeros and poles are highlighted in **(Table 2)** :

**Zeros/Poles Pairing and Ordering**

In Chapter 5 of *Analog MOS Integrated Circuits for Signal Processing* ^{1} , the calculation of pole-Q values in S-domain is illustrated. As for the pole-Q calculation in Z-domain, a direct way is to do the following:

assuming poles of *h(z)* can be represented as *Z _{i,i+1} = r_{i} * e^{+/-;θi } * in Z-plane. This will give an approximate value of each pole-Q.

A more accurate way of finding Q is mentioned in References 3 and 4. The authors of these papers have tried both methods during the pole-Q calculation. Since the pairing of numerators and denominators and the ordering of cascaded stages will affect signal-to-noise ratio (SNR), capacitance spread and sensitivities, an appropriate configuration is necessary.

The idea behind pairing of zeros and poles is described below. The most sensitive pole(s) (i.e. the one(s) closest to the unit circle in the Z-plane) will have the priority to be paired with the nearest zero(s), the second most sensitive pole(s) will be the next to be paired with nearby zeros, and so on. Following this rule, we've paired the poles and zeros. Three biquadratic sections can be found as follows:

where *C _{1} * C_{2} * C_{3} * = 0.00038221.

According to a rule of thumb, it is preferred to place the relatively higher-Q biquad(s) in the middle stage(s), and the relatively lower-Q biquads in the first and the last stages. From previous results, *H _{2} (z)* is placed in the middle stage.

There are two ways designers can choose to place the remaining two biquads. Since *Q _{3} &dt; Q_{1} * , we place the

*H*in the first stage and

_{1}(z)*H*in the third stage. This is a better configuration than placing

_{3}(z)*H*in the third stage and

_{1}(z)*H*in the first stage because a lower-Q section at the input stage will have better sensitivity performance and a lower capacitance spread. This has been proved by computer simulations.

_{3}(z)
After the dynamic range scaling, the first configuration gives a C_spread of 16.395, while the second one gives a value of 24.221. Hence, the ordering of the three biquads is: *H _{1} (z)* ,

*H*, and

_{2}(z)*H*. After ordering the biquads, we can plot the gain responses of each stage as shown in

_{3}(z)**Figure 3**.

**Dynamic Range Scaling and Optimal Capacitance Assignment**

Before entering the procedure of dynamic range scaling and capacitance optimization, the complete filter structure for SWITCAP^{5} simulation is shown in **Figure 4** .

*Step One: Dynamic Range Scaling (DRS)*

In order to achieve better dynamic range performance without overloading any of the six op amps into saturation, the maximum output voltage of each op amp is scaled to the same value.^{1} In Figure 4, we've scaled the output of each op amp to 1 V(0 dB) vs. a 1 V input. All capacitors connected to the output are scaled by the same value to set the op amp's output voltage to 1 V. **Figures 5** and **6** illustrate the output of each op amp before and after scaling.

Note that the results shown in Figure 5 and 6 were obtained without taking the constant gain factor (e.g. 0.00038221) into consideration. If the gain factor is not disregarded, the peaking in Figure 5 will be smaller.

The peak op amp output voltages are acquired from SWITCAP simulation using the structure in Figure 4, with “unscaled” (i.e. initial) capacitors and later with scaled capacitors. The SWITCAP program can be seen in the sidebar.

*Step Two: Optimal Capacitance Assignment*

In order to minimize the total capacitance and save chip area, the capacitances at the input terminal of each op amp can be normalized based on the smallest capacitance(s).^{1} . This is normally done by assigning the smallest capacitance as the unit capacitance (0.5pF in this project). The capacitance values acquired by using this scheme are shown in **Table 3** . The resulting capacitance spread is 16.3965 while the total capacitance value is 50.950 pF.

Nevertheless, the total capacitance in this case is not guaranteed to be minimum due to the fact that this capacitance minimization is carried out after the dynamic range scaling.^{4} . Several analytic techniques for realizing optimal capacitance assignment are available.^{2,3,4} For simplicity's sake, we make use of the algorithm for capacitance assignment in general lowpass biquad filters.^{4}

The biquads used in this project are of namely global type and local2 type. Through calculation in Matlab, the capacitance values are assigned as shown in Table 3. Matlab simulations, which use these new capacitance values instead of those acquired by assigning the smallest capacitance as 0.5 pF after dynamic range scaling (DRS), show similar frequency response compared to the previous scheme, but with a deviation of about 6 dB in the stopband gain. The resulting capacitance spread is 17.4394, while the total capacitance value is only 31.716 pF.

*Step Three: Minimize the Capacitance Spread*

A smaller capacitance spread means less influence of parasitic capacitance and a better sensitivity performance of the filter. By carrying out namely the T-network capacitor rearrangement, we can acquire a spread value, which is the square root of that before T-network rearrangement.

After the change, . The small capacitor can be replaced by a T-network containing three relatively bigger capacitors, CC1, CC2, and CC3, and:

Thus, the values of CC1s can be determined from Equation 6. After replacing all the small capacitors, spread value is decreased while the total capacitance value will be increased compared to that acquired from the conventional technique.^{1}

Results from the SWITCAP simulation after capacitance scaling (with op amp DC gain equal to 5000) are shown in **Figures 7** and **8** .

**Capacitor Mismatch Effect**

A capacitor mismatch random vector with std=0.1% is generated in Matlab. The new capacitor values that include the mismatch elements are sent to SWITCAP netlist. We can then simulate the effect of capacitor mismatch on the filter's performance, which is shown in **Figures 9** and **10** .

As Figures 9 and 10 show, the capacitor mismatch has little effect on gain response of the filter. However, it has forced the peaking in the passband to exceed 0.1 dB, which is not a trivial influence if we need the passband ripple to be less than 0.2 dB. For this project, the requirement *R _{p} * is less than or equal to 0.4 dB is still satisfied.

**Op Amp Requirements**

To meet the filter specification and achieve optimal performance, designers need to calculate the finite DC gain, finite bandwidth, and slew rate of the op amp. They also need to optimize the size of switches.

Let's look at how you calculate these three op amp parameters as well as switch size. We'll start with finite DC gain.

When finite op amp gain integrators are used in a biquad, the effect on the magnitude error m(w) would be to shift the pole frequency w_{o} to wo/1-1/A_{o} . For usual gain values less than 1000, this error is then negligible. However the phase error appears in the form of a pole-Q shift and is significant for high-Q biquads. The new pole-Q, designated Q', can be shown as:

where the factor '2' is due to two integrators in a biquad.

Due to the change in Q, there is an observed change in magnitude near the peak of the gain response .This error is given by Δα = 20log(1+2*Q* /A_{o} ). The observed magnitude peaking due to finite gain is plotted in **Figures 11** to **14** , with the opamp dc gain changing from 800 to 5000.

As can be seen from the above figures, a gain of at least 4000 (72dB) would be effective in suppressing the transfer function peaking in the passband near 1.5MHz.

**Finite Bandwidth**

In this article, the effect of finite bandwidth is analyzed with respect to the settling behavior of the circuit. In particular we will look at the time taken for the op amp in each of the biquads to settle. The op amp can be assumed to have widely separated poles, and a dominant single pole can be assumed to affect the frequency response. The op amp gain can then be written as:

where A_{o} is the DC gain and w_{o} is the unity gain bandwidth of the op amp.

In the time domain, this can also be written as:^{6}

V_{out} (t) is thus an exponential function during both the clock phases. The time constant (τ) depends on the capacitance values according to the discussion in the paragraphs to follow.

The output can be assumed to settle within 0.1% of its final value within 7τ. This settling time should be less than or equal to the pulse width of &phi_{2} phase (Equation 10).

Calculating the feedback factors of the op amps in the three biquads of our filter, we obtain the information in **Table 4** .

**Table 4. Feedback Factor of Every Integrator in Three Biquads**

Designing for worst-case scenario, the highest settling time is required by the op amp with lowest feedback factor (= 0.665). Substituting in the above equations, with sampling frequency = 30 MHz, we arrive at the relation that *W _{o} * is less than or equal to 134 MHz. In this article, we have designed the op amp for a unity gain bandwidth of 150 MHz.

SWITCAP simulations were carried out with varying bandwidth. For insufficient bandwidth, the op amp exhibits peaking in the passband. This results in unstable operation of the op amp as indicated in the transient simulation results shown below for an input frequency close to the passband edge. The effect can be ascribed to the ringing due to the bad settling behavior. The harmonics introduced by this are amplified and lead to unstable operation. The effect of finite bandwidth is seen in **Figures 15** , **16** , and **17** .

**Finite Slew Rate**

The slew rate refers to the rate at which the op amp can charge or discharge the op amp output capacitor. If the slew rate is so slow that the output voltage does not reach its final time within the clock phase, then non-linear distortion will take place.

The slew time of the op amp, determined by the slew rate of the op amp, is defined as *Tslew = ΔVout/Sr* , where , Sr is the slew rate given by:

To obtain an estimate of the ΔVout_{max} , assume an input voltage *v(t) = V* max*Sinw _{b} t* . To obtain the worst-case results, assume the w

_{b}is the highest possible frequency possible in the passband of the switched-capacitor filter and the amplitude is the largest voltage swing of the op amp (taken as Vdd for calculations ). The maximum slope possible is then given by:

The maximum step Vout(t) may then have to take every T =1/fc seconds is thus,

Δ*Vout* ,max = *w _{b} V* max/

*f*. Assigning a certain portion of the clock phase to the slewing time, T

_{c}_{slew}= xT(Φ

_{2}), the requirement on the op amp slew rate is then:

For the SC filter in this project, the minimum op amp slew rate required is 1.26 x 10^{9} V/s or 1260 V/μs which is pretty high .

**Switch Non-Idealities**

The switches realized using MOSFETs suffer from several non-idealities. One of the more significant ones is that of non-zero on resistance. When a device is operated in linear region, it behaves as a resistor of value . In a typical switched capacitor circuit, this switch is used to charge a capacitor to an input voltage V_{in} **(Figure 18)** .

The charging time need to reach V_{in} to an accuracy of 0.1% would depend on the resistor capacitor (RC) timing constant. The small signal settling time of the circuit of Figure 20 to within 0.1% of its final value of V_{out} is approximately 7τ i.e., 7R_{on} C.

The largest time constant of our filter involves the switch-C combination that transfers charges from a feed-forward path and input stage of the second op amp of the third-stage biquad (C_{b 3} ). The calculations indicate:

7(R_{on} C)_{max} = duration of single phase of clock

So the switch R_{on max} is approximately 220 ohm (Equation 14).

Assuming *(Vgs- Vt)* _{max} = 4 and *K* min = 5.68 x 10^{-4} , we receive:

Thus the W/L of the transistors can be really small. Transistor sizes of 10/1 were used in SPICE simulations.

**Transistor-level Implementation**

A brief description of the circuit blocks that were used in the simulations with a real op amp is given below.

In the filter design discussed in this article, we used the transmission gate as switch**(Figure 19 above)** . The size of transistor was chosen using:

We chose W/L ratio 20 for NMOS and 40 for PMOS to implement the transmission gate switch.

**Table 5: Gain Bandwidth and Phase Margin of Op Amp**

The top of the Figures 21 is the transient plot of transistor level filter and the bottom is the results showing the output of the filter when designed with an ideal op amp and switch. The input signal is a 1 MHz sine wave while the sampling frequency is 30 MHz.

In the real filter, peaking is observed to be more than that in the ideal case. A finite jump due to charge injection is also observed to occur at the falling edge of each clock phase.

**Non-Ideal Effects in Circuit Realization**

The finite gain and bandwidth effects have already been discussed above in the op amp requirement section. Now let's look at the other non-idealities that have been carried out along with verification with simulations. We'll start with channel charge injection.

The problem of charge injection can be explained in terms of a simple integrator switched capacitor circuit. Suppose an NMOS switch charges a capacitor C1 to the input voltage V_{in} when φ_{1} is high. This capacitor then discharges into the integrating capacitor during phase φ_{2} .

When the switch is closed during φ_{1} , a uniform conducting layer of electrons, with net charge Q_{ch} exists. Now when the switch S turns off, this charge find itself a discharge path to ground. So a portion of the charge (usually around half) enters C1, where it joins the signal charge C1V_{in} . This effect is “charge injection” and this can introduce non-linearity, gain error, and DC offset in the operation of the circuit.

For our switched-capacitor filter, the observed charge injection in the real op amp simulations is shown in **Figures 22** and **23** . The zoomed in portion shows the jump in the output voltage when φ_{2} turns off.

**Clock Feedthrough**

The clock feedthrough phenomenon arises as a result of the gate source and gate drain overlap capacitance of the switch device. So there is a capacitive coupling of the clock waveform into the signal path. The corresponding charge error is proportional to the parallel combination of the C_{ov} and the charging capacitor. This effect can be isolated by observing the output variations with zero input (see Figure 21 above).

In the switched-capacitor filter discussed here, we are exploiting the vital difference between charge injection and feedthroughthe former alone is input signal dependent and so, the latter may be isolated with no input voltage and just the clock switching. The initial portion of the clock feedthrough plot is due to the time taken for output to settle and is not due to feedthrough.

**DC Offset Voltage Effects**

The effect of DC offset was modeled by setting the biasing voltage of the negative input terminal of the opamp to a voltage slightly different from the other input. In our simulations, we had set the virtual ground of the op amp to 2.505 V (i.e. an input referred offset of 5 mV).

The effect of this offset on the output is obtained from the transient characteristic. Further a DC offset was also observed in the steady state when input was set to 0. The offset voltage also manifests itself in the form of a finite gain error as indicated in the plots below (**Figures 24 and 25** ).

**Wrap Up**

In this article, computer simulations are carried out to investigate how the circuitry non-idealities influence the performance of a switched-capacitor filter design. Optimum capacitance assignment techniques are also discussed that optimize the capacitor sizes and in turn to tight up the silicon chip area as well as the power budget.

**References**

- R. Gregorian and G. C. Temes,
*Analog MOS Integrated Circuits for Signal Processing*. New York: Wiley, 1986. - Q. Huang and W. Sansen, “Design techniques for improved capacitor area efficiency in switched-capacitor biquads,” IEEE Trans. Circuits Syst., vol. CAS-34, no. 12, pp.1590-1599, Dec, 1987.
- W. -H. Ki and G. C. Temes, “Area-efficient gain- and offset-compensated very large time-constant biquads,” Processing IEEE Int. Symp. On Circuits and System, pp. 1187-1190, 1992.
- W. -H. Ki and G. C. Temes, “Optimal capacitance assignment of switched-capacitor biquads,” IEEE Trans. Circuits Syst.-I: Funde. Theory and Applic. Vol. 42. No. 5, pp. 334-342, June 1995.
- User's Guide for SWITCAP Version 5, Columbia Univ., 1987.
- G. C. Temes, “Finite Amplifier Gain and Bandwidth Effect in Switched-capacitor Filters,” IEEE JSSC.,Vol. SC-15, No.3, June 1980.

**About the Author**

**Mingliang Liu** is a product development manager at Extron Electronics. Prior to this position, he served as a product manager at AV Link, Inc. He holds a B.S.E.E. degree from Beijing Institute of Technology and a M.S.E.E. degree from Oregon State University. Mingliang can be reached at .

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